GaN DEVICE WITH REDUCED OUTPUT CAPACITANCE AND PROCESS FOR MAKING SAME

ABSTRACT

A GaN transistor with reduced output capacitance and a method form manufacturing the same. The GaN transistor device includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.61/859,508, filed on Jul. 29, 2013, the entire disclosure of which ishereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to transistors, and, moreparticularly to a GaN transistor with reduced output capacitance.

2. Description of the Related Art

Conventional transistor devices generally experience some level oftransistor power dissipation due to conduction loss and switching loss.When transistors operate at higher frequencies, it becomes even moreimportant to reduce switching loss. Additionally, in hard switchingcircuits, charging and discharging the output capacitor in every switchcycle influences the power dissipation of the transistor device.

Output capacitance (“Coss”) is the summation of gate-drain capacitanceand source-drain capacitance. FIG. 1 schematically illustrates the Cossvs. drain-source voltage curve of a conventional GaN transistor as adashed line.

FIG. 2( a) depicts a cross-sectional view of a conventional GaNtransistor 101 when the drain-source voltage is at 0 volts. As shown,the GaN transistor 101 includes a substrate 109, buffer layers 110formed on the substrate 109, and a two dimensional electron gas (“2DEG”)formed just below a barrier layer 104. Furthermore, the GaN transistor101 includes a source electrode 102, a gate electrode 103, a drainelectrode 105, a field plate 106 and a dielectric film 107.

In operation, when the drain-source voltage is at 0 volts, the Cosscomponents of the GaN transistor 101 include a capacitor (“C1”) betweenthe gate 103 and the drain side 2DEG 111, a capacitor (“C2”) between thefield plate 106 and the drain side 2DEG 111, and a capacitor (“C3”)between the substrate 109 and the drain side 2DEG 111. When thedrain-source voltage is at 0 volts, the capacitors C1, C2, and C3 are attheir highest values.

FIG. 2( b) depicts a cross-sectional view of the conventional GaNtransistor 101 when the drain-source voltage is a high voltage. Asdrain-source voltages increase, the drain side 2DEG 111 depletes towardthe drain contact 105; C1 and C2 approach zero; and C3 decreases.

A primary objective of this invention is to reduce the outputcapacitance Coss of a transistor while maintaining gate width, whicheffectively reduces power dissipation, and, therefore, increasesfrequency capability in RF amplifiers that include such transistors.

SUMMARY OF THE INVENTION

Embodiments described below address the problems discussed above andother problems, by providing manufacturing method of GaN semiconductordevices that include an isolation region in the transistor device thatremoves a portion of the 2DEG to reduce output capacitance Coss of thedevice.

The GaN transistor disclosed includes a substrate layer, one or morebuffer layer disposed on a substrate layer, a barrier layer disposed onthe buffer layers, and a two dimensional electron gas (2DEG) formed atan interface between the barrier layer and the buffer layer.Furthermore, a gate electrode is disposed on the barrier layer and adielectric layer is disposed on the gate electrode and the barrierlayer. The GaN transistor includes one or more isolation regions formedin a portion of the interface between the at least one buffer layer andthe barrier layer to remove the 2DEG in order to reduce outputcapacitance Coss of the GaN transistor.

Furthermore, a method for fabricating a GaN transistor device asdescribed herein includes the steps of forming at least one buffer layeron a substrate layer; forming a barrier layer on the at least one bufferlayer with a two dimensional electron gas (2DEG) disposed at aninterface between the barrier layer and the buffer layer; forming a gateelectrode on the barrier layer; and forming a first isolation region ina portion of the interface between the at least one buffer layer and thebarrier layer to remove the 2DEG from the portion of the interface wherethe isolation region is formed.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, objects, and advantages of the present disclosure willbecome more apparent from the detailed description set forth below whentaken in conjunction with the drawings in which like referencecharacters identify correspondingly throughout and wherein:

FIG. 1 schematically illustrates the Coss vs. drain-source voltage curveof a conventional GaN transistor as a dashed line.

FIG. 2( a) illustrates a cross-sectional view of a conventional GaNtransistor when drain-source voltage is at 0 volts.

FIG. 2( b) illustrates a cross-sectional view of a conventional GaNtransistor when drain-source voltage is at a high voltage.

FIG. 3( a) illustrates a schematic top view of a GaN transistor withreduced Coss in accordance with an exemplary embodiment of the presentinvention.

FIG. 3( b) illustrates a cross-sectional view A-A of the GaN transistorof FIG. 3( a) in accordance with an exemplary embodiment of the presentinvention.

FIG. 3( c) illustrates a cross-sectional view B-B of the GaN transistorof FIG. 3( a) in accordance with an exemplary embodiment of the presentinvention.

FIGS. 4( a)-4(e) depict a fabrication process of a GaN transistor of thepresent invention with reduced Coss.

FIG. 5 schematically illustrates the Coss vs. drain-source voltage curveof a conventional GaN transistor compared with a GaN transistoraccording to an exemplary embodiment of the present invention.

The figures are not necessarily drawn to scale and the elements ofsimilar structures or functions are generally represented by likereference numerals for illustrative purposes throughout the figures. Thefigures are only intended to facilitate the description of the variousembodiments described herein; the figures do not describe every aspectof the teachings disclosed herein and do not limit the scope of theclaims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description, reference is made to certainembodiments. This detailed description is merely intended to teach aperson of skill in the art further details for practicing preferredaspects of the present teachings and is not intended to limit the scopeof the claims. Therefore, combinations of features disclosed in thefollowing detailed description may not be necessary to practice theteachings in the broadest sense, and are instead taught merely todescribe particularly representative examples of the present teachings.It is to be understood that other embodiments may be employed and thatvarious structural, logical, and electrical changes may be made.

FIGS. 3( a)-3(c) illustrate a GaN device 201 with reduced Coss accordingto a first exemplary embodiment of the present invention. As shown inFIG. 3( b), the GaN device 201 is formed on a substrate 209, which canbe silicon (Si), silicon carbide (SiC) or sapphire, for example. One ormore buffer layers 210 are formed on the substrate 209 and can includegallium nitride (GaN), aluminum nitride (AlN) and aluminum galliumnitride (AlGaN). In the exemplary embodiment, one of the buffer layers(i.e., the buffer layer closest to a barrier layer 204) is a channellayer, which is preferably composed of gallium nitride (GAN). It shouldbe understood that the channel layer can be consider as one of thebuffer layers or as a separate layer between the buffer layers and thebarrier layer. The barrier layer 204 is formed over the buffer layers210, with the two dimensional electron gas (“2DEG”) 211 formed at theinterface between the buffer layers 210 and the barrier layer 204. Forexample, if the buffer layers 210 include a channel layer formed of GaN,the 2DEG region is formed at the interface between the GaN layer and thebarrier layer 210. A dielectric layer 207 is deposited on the barrierlayer 204.

FIGS. 3( a) and 3(b) illustrate the GaN device 201 that further includesa source electrode 202, a gate electrode 203, a drain electrode 205 anda field plate 206. In order to reduce Coss of capacitor C2, which wasdiscussed above with reference to FIG. 2( a), a first isolation region301 is formed under the field plate 206. Although not shown in FIG. 3(a), in one refinement of this embodiment the isolation region 301 canfully extend to the gate electrode 203 to deplete the gate to fieldplate region and reduce the capacitance C_(gd), which is included inCoss.

As further shown in FIG. 3( a), a second isolation region 302 can beformed outside of the field plate 206 towards the drain contact 205 toreduce the Coss of capacitor C3, according to another exemplaryembodiment of the present invention. In addition, a third isolationregion 303 is formed, similar to isolation region 302, but also extendsthrough the drain contact 205, with part of drain contact 205 removed.Isolation region 303 also reduces the Coss of capacitor C3, discussedabove.

It should be appreciated that each of isolation regions 301, 302, and303 are formed in the buffer layer 210 of the GaN device 201 and thatthe 2DEG is removed where the isolation regions are formed. Inparticular, FIG. 3( b) illustrates a cross-sectional view A-A of FIG. 3(a) that shows first isolation region 301 where the 2DEG is removed. Asnoted above, this isolation region 301 reduces Coss of capacitor C2,which was discussed above with reference to FIG. 2( a). Similarly, FIG.3( c) illustrates a cross-sectional view B-B of FIG. 3( a) that showsthe third isolation region 303 where the 2DEG is removed and a portionof the drain contact 205 is removed. It is noted that the layers of theGaN device 201 that are illustrated in FIGS. 3( b) and 3(c) areidentical to those layer shown in FIG. 3( a) and are given identicalreference characters, and detailed descriptions thereof will not berepeated herein.

In view of FIGS. 3( a)-3(c), it is contemplated that at least fiveseparate embodiments of a GaN transistor device with reduced outputcapacitance are provided herein. A first embodiment includes isolationregion 301 formed under field plate 206, as shown in FIGS. 3( a) and3(b), for example. A second embodiment is to form isolation regionsoutside of the field plate and towards the drain contact 205, e.g.,isolation regions 302 as illustrated in FIG. 3( a). As noted above,isolation region 302 reduces capacitance C3. A third embodiment is toform isolations regions 303 as shown in FIGS. 3( a) and 3(c), whichremoves a fraction of the drain contacts 205 and extends outside of thedrain contact 205. Forming isolation region 303 also reduces capacitanceC3. It should be appreciated that a fourth embodiment would include aGaN device 201 that includes two or more of isolation regions 301, 302,and 303. Finally, a fifth embodiment of the present invention is toinclude an isolation region under the field plate 206 and a voltageindependent capacitor that Coss is more flat over a wider range of drainvoltages.

It is noted that forming isolation regions 301, 302 and 303 results inan increased Rds(on). Accordingly, in one refinement of the exemplaryembodiment, the area of the isolation regions are optimized to minimizepower dissipation. In this instance, the product of Rds(on) and Eoss canbe used as a figure of merit in this optimization. The optimalpercentage area for the isolation area depends upon the voltage ratingof the device, and the materials and layout parameters of the device.

FIGS. 4( a)-(e) illustrate an exemplary manufacturing process for a GaNdevice with reduced output capacitance Coss according to an exemplaryembodiment of the present invention. As shown in FIG. 4( a), a substratelayer 209 is created. As noted above, substrate layer 209 can be formedfrom, silicon (Si), silicon carbide (SiC), sapphire or the like. Next,buffer layers 210 are deposited above substrate 209. The buffer layers210 can include gallium nitride (GaN), aluminum nitride (AlN) andaluminum gallium nitride (AlGaN). Next, a barrier layer 204 may beformed above the buffer layers 210. As noted above, the two dimensionalelectron gas (“2DEG”) is formed at the interface between the bufferlayer 210 and the barrier layer 204. Finally, a gate layer 212 can beformed above the barrier layer 204. It should be appreciated that thelayer forming steps can be performed using any conventional depositiontechnique, such as atomic layer deposition or plasma enhanced chemicalvapor deposition or the like.

Next, as shown in FIG. 4( b), a pattern is placed on the gate layer 212and etched to form the gate electrode 203. Once the gate electrode 203is formed, one or more of isolation regions 301, 302, or 303 can beformed in the GaN device 201 as illustrated FIG. 4( c). While FIG. 4( c)only illustrates the forming of isolation region 301 for exemplarypurposes, it should be appreciated that one or more of the threeisolation regions 301, 302, or 303 can be formed during this step.Furthermore, in the exemplary embodiment, isolation regions 301, 302,and/or 303 are formed by ion implantation or etching.

As shown in FIG. 4( d), a dielectric film 207 is deposited over barrierlayer 204 and gate electrode 203 once the isolation regions 301, 302,and/or 303 are formed. FIG. 4( d) further illustrates the formation ofopenings for the source 202 and drain 205 contacts by patterning andetching. Finally, as shown in FIG. 4( e), the Ohmic contact metals forthe source 202 and drain 205 contacts are deposited, patterned, andetched. Additionally, the field plate 206 is developed for GaN device201, which is then treated to a rapid thermal annealing (RTA).

FIG. 5 schematically illustrates the Coss vs. drain-source voltage curveof a conventional GaN transistor compared with a GaN transistoraccording to an exemplary embodiment of the present invention. As notedabove with respect to FIG. 1, the Coss vs. drain-source voltage curve ofa conventional GaN transistor is illustrated as a dashed line. Anachieved object of this inventive GaN transistor 201 is to shift thecurve down and to the left, that is, from the dashed line to the solidline, i.e., to decrease Coss. Thus, the Coss vs. drain-source voltagecurve of the inventive GaN transistor is illustrated as the solid line.

The above description and drawings are only to be consideredillustrative of specific embodiments, which achieve the features andadvantages described herein. Modifications and substitutions to specificprocess conditions can be made. For example, in addition to GaNtechnology, the present invention can be applied to LDMOS as well bydepleting or not creating similar patterns in the LDD. Accordingly, theembodiments of the invention are not considered as being limited by theforegoing description and drawings.

What is claimed is:
 1. A transistor device comprising: at least onebuffer layer disposed on a substrate layer; a barrier layer disposed onthe at least one buffer layer with a two dimensional electron gas (2DEG)disposed at an interface between the barrier layer and the buffer layer;a gate electrode disposed on the barrier layer; a dielectric layerdisposed on the gate electrode and the barrier layer; an isolationregion formed in a portion of the interface between the at least onebuffer layer and the barrier layer, such that the 2DEG is removed fromthe portion of the interface where the isolation region is formed. 2.The transistor device according to claim 1, further comprising a fieldplate disposed on the dielectric layer, wherein at least a portion ofthe isolation region is formed under the field plate.
 3. The transistordevice according to claim 1, further comprising source and draincontacts disposed above the barrier layer.
 4. The transistor deviceaccording to claim 3, wherein at least a portion of the isolation regionis formed under the drain contact.
 5. The transistor device according toclaim 4, wherein at least a portion of the isolation region extendsthrough a portion of the drain contact.
 6. The transistor deviceaccording to claim 1, wherein the isolation region extends into the atleast one buffer layer towards the substrate layer and further extendsinto the barrier layer towards the dielectric layer.
 7. A transistordevice comprising: at least one buffer layer disposed on a substratelayer; a barrier layer disposed on the at least one buffer layer with atwo dimensional electron gas (2DEG) disposed at an interface between thebarrier layer and the buffer layer; gate electrode disposed on thebarrier layer; a dielectric layer disposed on the gate electrode and thebarrier layer; a first isolation region and a second isolation regioneach formed in respective first and second portions of the interfacebetween the at least one buffer layer and the barrier layer, such thatthe 2DEG is removed from the first and second portions of the interfacewhere the isolation region is formed.
 8. The transistor device accordingto claim 7, further comprising a field plate disposed on the dielectriclayer, wherein at least a portion of the first isolation region isformed under the field plate.
 9. The transistor device according toclaim 8, further comprising source and drain contacts disposed above thebarrier layer.
 10. The transistor device according to claim 9, whereinat least a portion of the second isolation region is formed under thedrain contact.
 11. The transistor device according to claim 10, whereinat least a portion of the second isolation region extends through aportion of the drain contact.
 12. A method for fabricating a transistordevice, the method comprising: forming at least one buffer layer on asubstrate layer; forming a barrier layer on the at least one bufferlayer with a two dimensional electron gas (2DEG) disposed at aninterface between the barrier layer and the buffer layer; forming a gateelectrode on the barrier layer; and forming a first isolation region ina portion of the interface between the at least one buffer layer and thebarrier layer to remove the 2DEG from the portion of the interface wherethe isolation region is formed.
 13. The method according to claim 12,further comprising depositing a dielectric layer over the gate electrodeand the barrier layer.
 14. The method according to claim 13, furthercomprising forming a field plate on the dielectric layer above the firstisolation region.
 15. The method according to claim 12, furthercomprising forming a second isolation region in another portion of theinterface between the at least one buffer layer and the barrier layer.16. The method according to claim 15, further comprising depositing adielectric layer over the gate electrode and the barrier layer.
 17. Themethod according to claim 16, further comprising forming a field plateon the dielectric layer above the first isolation region.
 18. The methodaccording to claim 17, further comprising patterning and etching thedielectric layer to form openings for drain and source contacts.
 19. Themethod according to claim 18, further comprising depositing ohmiccontact metal in the openings to form the drain and source contacts. 20.The method according to claim 19, wherein the second isolation region isformed below the drain contact.
 21. The method according to claim 20,wherein at least a portion of the second isolation region extendsthrough a portion of the drain contact.